Fully self aligned architectures in bipolar transistors are advantageous is that they provide better window downscaling and lower levels of parasitic capacitances and parasitic resistances. A critical step in the formation of a fully self aligned bipolar transistor is the formation of a cavity for the selective epitaxial growth (SEG) of the base portion of the transistor. For example, consider the prior art method for manufacturing a fully self aligned bipolar transistor shown in FIG. 1 and in FIG. 2.
FIG. 1 illustrates a schematic diagram of a cross section of an intermediate structure 100 formed during the manufacture of a prior art fully self aligned bipolar transistor showing a cavity formed over the collector portion of the transistor. The intermediate structure 100 shown in FIG. 1 comprises a Non-Selective Epitaxial Growth (NSEG) collector 110 and a selective implanted collector (SIC) 120 located within a central portion of the NSEG collector 110. The central portion of the NSEG collector 110 is located between two shallow trench isolation (STI) structures 130. During the manufacture of the intermediate structure 100 shown in FIG. 1, a layer of silicon oxide 140 (e.g., tetraethyloxysilane 140) is placed over the NSEG collector 110 and over the STI structures 130.
Then a layer of in-situ doped polysilicon material 150 is placed over the layer of silicon oxide 140 to form a raised external base. Then a first layer of silicon nitride 170a is formed over the polysilicon material 150. Then a mask and etch procedure is applied to etch through the central portion of first layer of silicon nitride 170a and through the central portion of the polysilicon material 150 to form an emitter window 160. The etch procedure stops on the layer of silicon oxide 140.
Then a second layer of silicon nitride 170b is placed over the first layer of silicon nitride 170a and over the layer of silicon oxide 140. The second layer of silicon nitride 170b covers the side walls of the emitter window 160. The first layer of silicon nitride 170a and the second layer of silicon nitride 170b merge to form a layer of silicon nitride (designated with reference numeral 170). The silicon nitride 170 forms a nitride spacer. Then an unmasked etch procedure is performed to etch the second layer of silicon nitride 170b down to the silicon oxide 140.
Then a diluted hydrofluoric acid (HF) etch procedure is applied to etch laterally through the layer of silicon oxide 140 to form a cavity 180. That is, the portions of the layer of silicon oxide 140 that are etched away are removed to form cavity 180. As will be described below, the cavity 180 will receive a layer of monocrystalline silicon to form a base structure over the NSEG collector 110. The resulting intermediate structure 100 is shown in FIG. 1.
FIG. 2 illustrates a schematic diagram of a cross section of the intermediate structure 100 shown in FIG. 1 following the selective epitaxial growth (SEG) of a layer of monocrystalline silicon 210 in the cavity 180. The resulting intermediate structure is designated with reference numeral 200. As shown in FIG. 2, the top portions of the SEG monocrystalline silicon 210 grow upwardly and come in contact with downwardly growing portions of the polysilicon material 150. The contact surface of the two structures is designated with reference numeral 220 in FIG. 2.
It is very important that there be a contiguous connection between the polysilicon material 150 and the monocrystalline silicon 210 at the surface 220. A contiguous connection is required in order to minimize the magnitude of the base resistance. If there are gaps or other irregularities at the surface 220, there will be an undesirable increase in the magnitude of the base resistance.
It is also very important that there be a sufficient amount of boron diffusion from the highly doped polysilicon material 150 of the raised external base into the base-collector corner. A sufficient amount of boron diffusion is required in order to minimize the magnitude of the base-collector current. If there is an insufficient amount of boron diffusion into the base-collector corner, there will be an undesirable increase in the magnitude of the base-collector current. Ensuring that a sufficient amount of boron diffusion is present is particularly important for an advanced Bipolar-Complementary Metal Oxide Semiconductor (BiCMOS) process with a reduced rapid thermal anneal (RTA).
Prior art fully self aligned bipolar transistors sometimes do not have a completely contiguous connection at the surfaces between the polysilicon material of the raised external base and the monocrystalline silicon of the base. Prior art fully self aligned bipolar transistors sometimes do not allow a sufficient amount of boron to diffuse from the highly doped polysilicon material of the raised external base into the base-collector corner of the transistor.
Therefore, there is a need in the art for a system and method that is capable of solving the problems that occur when such prior art methods are utilized. In particular, there is a need in the art for a system and method for providing an efficient process that is capable of manufacturing a fully self aligned bipolar transistor that has a modified cavity formation that optimizes the selective epitaxial growth (SEG) of a monocrystalline silicon base of the transistor.
The method of the present invention solves the problems that are associated with the prior art by providing a cavity that has a shape that increases the likelihood that a contiguous connection will be formed at the surfaces between the polysilicon material of the raised external base and the monocrystalline silicon of the base. The method of the present invention also provides a cavity that has a shape that increases the likelihood that a sufficient amount of boron will be able to diffuse from the highly doped polysilicon material of the raised external base into the base-collector corner of the transistor.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.